Wie schützt man die Gate-Oxidschicht eines MOSFET vor Durchbruch?
The SiO₂ oxide layer between the gate and source of a MOSFET is the core of the device, with a thickness of only a few nanometers. Once the voltage exceeds the threshold (±30V for Si MOSFET, +30V/-10V for SiC MOSFET), permanent breakdown will occur. Leiditech EMC Team found in hundreds of energy storage and industrial control projects that 70% of MOSFET failures were related to surge breakdown of the gate oxide layer, and this failure was completely irreversible.
VGS overvoltage: A Fatal Threat of Transient Surges

MOSFET have a clear limit on the VGS voltage: the steady-state voltage is commonly ±20V (partially ±30V), the transient voltage is mostly ±30V, and the actual drive voltage is mostly between 12V and 15V. However, NS-level transient surges caused by ESD static electricity, disconnection of inductive loads, and parasitic inductive coupling of PCBS can easily lead to VGS exceeding the limit.
This type of impact can damage the ultrathin oxide layer of the gate through the Fowler-Nordheim tunneling effect, leading to an increase in on-resistance, threshold voltage drift, and a rise in gate leakage current. Eventually, it manifests as abnormal switching and increased static power consumption and other faults. Unlike drain avalanche breakdown, the gate oxide layer has no energy absorption capacity, and breakdown means the device is scrapped.
TVS selection: Total Solution for Precise Protection

1. Non-negative pressure drive scenario: Unidirectional TVS is preferred
- Negative clamping is equivalent to the forward conduction voltage drop of the diode (Vf=0.7V), and its protection effect is superior to that of bidirectional TVS
- Typical VRWM selection: 15V ~ 18V, VC range 24.4V ~ 29.2V

2. The application of TVS within negative voltage drive: Select bidirectional TVS
- The Leiditech bidirectional TVS features symmetrical clamping characteristics, capable of simultaneously protecting against positive and negative overvoltage, and is suitable for complex driving requirements.

3. SiC MOSFET:Asymmetric protection scheme
The negative withstand voltage of SiC MOSFETs is only -10V, and they are prone to parameter degradation due to high electric field stress. Targeted protection is required. Leiditech Electronic has launched an asymmetric TVS protection solution, which perfectly meets the requirements of SiC MOSFETs through a differentiated clamping design in the positive and negative directions
- Positive: VRWM=15V ~ 20V, VC=18.57V ~ 26.40V (@Ipp)
- Negative: VRWM=-6V, VC=-10.3V (@Ipp)
|
Leiditech TVS Bi |
Leiditech TVS Uni |
Reverse working voltage max Vrwm (V) |
Breakdown voltage VB(V) |
Clamping voltage VC(V) |
Maximum peak pulse current Ipp(A) |
|
SMBJ15CA |
SMBJ15A |
15 |
16.7~18.5 |
24.4 |
24.6 |
|
SMBJ16CA |
SMBJ16A |
16 |
17.8~19.7 |
26.0 |
23.1 |
|
SMBJ18CA |
SMBJ18A |
18 |
20.0~22.1 |
29.2 |
20.6 |
|
SMBJ6.0CA |
SMBJ6.0A |
6 |
6.67-7.37 |
10.3 |
58.3 |
The gate protection of MOSFETs needs to be precisely designed based on failure mechanisms. Leiditech Electronic covers the protection requirements of general MOSFETs and SiC MOSFETs through unidirectional and bidirectional TVS part numbers, providing full-process technical support from selection to application.
Shanghai Leiditech Electronic is committed to becoming a leading brand in electromagnetic compatibility solutions and component supply, offering products such as ESD, TVS, TSS, GDT, MOV, MOSFET, Zener, inductors, etc. Leiditech has an experienced R&D team that can provide personalized customization services tailored to customer requirements and deliver the highest-quality solutions.
Hinterlasse eine Antwort
- Circuit Protection Primer: The Art of Shielding from ESD to Surge
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- Regarding the domestic substitution of PESD5VOHS-SF and ESD7501MUT5G with ULCO521CLV
- Component-Level ESD vs. System-Level ESD — A Must-Know for Hardware Engineers
